Background

On this page, I furnish a few observations and assorted (simulation &) experimental results obtained from my hardware setups during my research career across master's, Ph.D., and postdoc stints, which I personally found to be instructive & exciting.

State-feedback Inverter Control

System setting: A single-phase H-bridge PWM inverter with output LC filter (switched via unipolar PWM, Fsw = 10kHz, Vo = 120V rms) under full state-feedback control. Inductor current and capacitor voltages are the two states, that are controlled via the two feedback gains, k1, k2. 

Comment: The result above compares the start-up transient performance showing output-filter capacitor voltage and current for (a) full-order switched model simulation in Matlab-Simulink, and (b) hardware experiment. A very close match between the simulation model and experimental result can be noted, which demonstrates the high accuracy of the developed switched model with closed-loop control.

Effect of ADC Sampling Rate on Control Performance

System setting: A single-phase H-bridge PWM inverter with output LC filter (switched via unipolar PWM, Fsw = 10kHz, Vo = 120V rms) under full state-feedback control. Inductor current and capacitor voltages are the two states, that are controlled via the two state-feedback gains, k1, k2. 

Comment: The result above compares the steady-state profiles of output-filter capacitor current for (a) ADC single sampling (at carrier peak only), and (b) ADC double sampling (at both carrier peak and valley). Under high control-bandwidth conditions, note that the single-sampling case displays higher oscillations in the current (a controlled variable) as compared to the double-sampling case, indicating poorer phase margin in the former case due to the added digital delay.

SRF-PLL Synchronization Behavior

System setting: Three-phase grid voltage sensed and fed to SRF-PLL (implemented in DSP). The estimated grid frequency (output via DAC, shown as blue trace) along with the enable signal (pink trace) for the PLL is shown above for two cases of bandwidth choices.

Comment: Under low-bandwidth conditions, when the PLL is enabled, one can note the dynamic evolution of the estimated frequency signal to contain an uncharacteristic oscillatory behavior, which is indicative of the nonlinear nature of the SRF-PLL control loop. Under high-bandwidth conditions, the inherent nonlinearity is subsumed by the high-gain controller and we obtain a more familiar type of tracking behavior (when PLL is enabled) with some overshoot in response before synchronizing with the grid frequency.

Grid-following (GFL) PV Inverter performance with LCL-filter

System setting: A single-phase H-bridge PWM inverter with output LCL filter operated as a GFL PV inverter (switched via unipolar PWM, Fsw = 10kHz, Vpv = 480V (occ), Vg = 190V rms) with Resonant PLL and PR current controller. The inverter is fed from an actual rooftop PV source (see here).

Comment: This result demonstrates the GFL dynamic behavior; presented above is a comparison of transient performance of the current-control loop (for a real-current-reference command change) showcasing inverter-side, grid-side, and PV currents for (a), the full-order switched model simulation in Matlab-Simulink, and (b) hardware experiment. The inverter-side current contains switching PWM harmonics while the injected grid current is devoid of the same. In particular, the DC-side PV current is noted to carry the double line frequency (100Hz) ripple that is characteristic to single-phase inverter systems.

P&O MPPT Operation in a PV-fed PWM converter

System setting: A single-phase H-bridge PWM converter with output LCL filter (switched via unipolar PWM, Fsw = 10kHz, Vpv = 480V (occ)) operated in two modes: (a) as a GFL inverter feeding the grid (Vg = 190V rms), and (b) as a DC-DC charge controller feeding a battery bank (200V). The inverter is fed from an actual rooftop PV source (see here).

Comment: In Fig. (a), the system is operated as a GFL inverter connected to the grid and performing P&O MPPT; the slow and steady increase in the AC current amplitude can be noted along with the 100Hz ripple (seen on the dc side as a band riding) on both the PV voltage and current. In Fig. (b), the system is operated as a dc-dc charge controller connected to a battery bank and performing P&O MPPT; the slow and steady increase in the filter inductor current magnitude and ultimately settling at the MPP value can be noted. One can also note the absence of 100Hz ripple on the dc side in PV voltage and current

[See here for further details.]

Islanding behavior of GFL Inverter with RLC load bank

System setting: A three-phase 2L PWM  inverter with output LCL filter is operated a GFL inverter (Fsw = 10kHz, Vdc = 800V, Vg = 190V rms) with PI-based current controllers in dq-frame. The GFL is initially grid-tied and subsequently islanded (by intentionally opening the grid breaker), and the observed profile of the PCC voltage is showcased here.

[See here for further details.]

Active Impedance Characterization of Solar PV panel

System setting: Rooftop experimentation performing active frequency-sweep measurements on a single 300Wp, 45Vocc, monocrystalline PV panel, for differential- and common-mode impedance characterization across different operating currents (from OCC to near-MPP current). Characterization was performed using a frequency-response analyzer (FRA) and (an appropriately designed) decoupling circuit to interface FRA with the PV panel. 

Comment: The measured DM impedance, as shown in Fig. (a), indicates a largely resistive behavior at low frequencies and later dominated by an inductive behavior (that is inferred to be arising intrinsically by virtue of the metallic interconnects present inside the panel). On the other hand, the CM impedance (measured on both positive- and negative-PV terminals w.r.t power earth)  shown in Fig. (b) indicates a dominantly capacitive behavior, capturing the ground coupling capacitance of the panel.

[See here and here for more details.]

Ultracapacitor storage bank characteristics

System setting: A 4 kW-min UC bank with 224 UC cells (each of 310F capacitance) is characterized; discharge behavior from 600V at constant-current and constant-power conditions, respectively, are shown.

Comment: The UC is a nonlinear component intrinsically displaying voltage-dependent capacitance characteristics. The plot on the left indicates the total UC-bank capacitance with 224 cells in series showing the experimentally measured vs analytically estimated profiles (the nonlinear parameters of a single UC cell are leveraged to estimate the total bank capacitance characteristics by appropriate scaling). Waveforms in Fig. (a) and Fig. (b) show the discharge voltage profiles under constant-current (CC) and constant-power (CP) mode of operation. By virtue of the nonlinear nature of the UCs, we obtain more (effective bank capacitance and) backup time in practice from the storage bank than what is calculated from the design based on the linear assumption (i.e. Ceff = 310F/224).

[See here for further details.]

Integrated-magnetic Filter Transformer

System setting: Fig. (a) shows a single-phase 3 kVA integrated-magnetic filter transformer (IMFT) structure that provides galvanic isolation as well as functions as a higher-order PWM filter for an inverter. In this experiment, the IMFT is operated in the grid-tied mode via a single-phase 2L H-bridge inverter (Vdc = 400V, Fsw = 10kHz), and its performance is examined. 

[The IMFT is built as a shell-type transformer with three windings; the primary and secondary are sized for the inverter current rating and provide the necessary galvanic isolation; a third tertiary winding is present that is connected in parallel with the primary winding along with an external capacitor. The tertiary winding provides the filtering action similar to an LCL filter in the desired frequency range and is rated for just the PWM ripple current. The IMFT is built from amorphous cores that have superior loss characteristics and higher saturation flux density. 

A salient attribute of the IMFT is that I built this prototype in the laboratory by assembling the C cores inside a bobbin hand-cut-and-glued with hylam sheets, and hand-wound the windings using a transformer winding machine.

See here for more details. ]

Comment: The LCL-filter action of the IMFT (for attenuating PWM ripple) can be observed in the measured grid-current transfer function as shown in Fig. (b) (on the top). When deployed with a grid-tied PWM inverter that is injecting real current into the grid (see results in Fig. (b)), the presence & absence of PWM ripple current can be noted in the inverter & grid currents, respectively. With such an integrated-magentic structure in place, there is no need to employ a separate LCL filter on a PWM converter for grid connection and filtering purposes. The leakage inductances of the IMFT (along with an external filter capacitor) are leveraged to achieve the required LCL filtering action. 

Double-pulse Device Switching Characterization

System setting: Device-switching characterization performed using double-pulse test conducted with the aid of GPDCS for a comparative study of devices. A set of similarly-rated (1200V, 50A) state-of-the-art devices from three different manufacturers are chosen, which includes two Silicon IGBTs and one SiC MOSFET.  Test conditions are identical for all cases---gate resistance of 12Ohms, 800V dc-bus voltage, and 40A drain current at ambient 27degC. Device current measured via Rogowski current probe.

[Tests were also carried out at elevated temperatures of 125degC and 175degC for a thorough comparative study. See here for further details.]

Comment: One can observe and compare the behavior of: (a) turn-on current overshoot due to diode reverse recovery, (b) turn-off voltage excursion across the device, and subsequent oscillations due to circuit parasitics, (c) Miller plateau in gate voltage, and (d) parasitic inductance voltage drop (Lp*di/dt ) in the device voltage during the current rise. It can be noted that while the SiC device switches faster, it also exhibits much greater oscillations than the Si device.

Frequency Response Characterization of Capacitors

System setting: Experimental frequency-sweep impedance measurements on different types of passive capacitors commonly employed in power-electronics applications: (a) 30uF EPCOS metalized polypropylene (MPP) AC filter capacitor (typically used in inverter output), (b) 820uF Würth snap-in Al electrolytic capacitor (typically used in inverter DC-links), and (c) 310F Maxwell snap-in Ultracapacitor (typically used in energy storage banks). Characterization was performed using a frequency-response analyzer (FRA).

Comment: Note that the capacitor parasitics (i.e., the ESR & ESL) start to dominate the impedance characteristics beyond (a) 50kHz in case of the MPP filter cap (displaying resonance in the bode plot); (b) 2kHz in case of the electrolytic cap; (c) 1Hz in case of UC. In this comparison, it is apparent that the electrolytic cap has the highest ESR value compared to the other capacitor types. These plots provide insights into the approximate circuit model (in the control bandwidth frequency range) that can be employed for capacitors, thus simplifying control design. (E.g., the UC model can simply be a resistor for the purpose of control, thus simplifying the dynamic plant model for analysis and synthesis.)

Common Nonlinear (domestic) Loads

System setting: Experimental measurements of AC currents drawn from mains by three types of nonlinear loads commonly found in domestic settings: (a) 15W CFL lightbulb, (b) 35W 24" LCD monitor, and (c) 20W LED tube light (with PFC feature).

Comment: As can be noted, the CFL and LCD monitors have fairly spiky currents caused by the peak charging of the DC capacitors present in the rectifier stage at the input. In the case of LED tube light (that claims PFC), however, the currents are quite smooth; but notably, currents are flat zero for more than 2 ms in each half cycle (near zero crossings). Most likely, a passive higher-order input filter (a typical low-cost solution) is employed to smoothen out the current and improve the power factor.